(China (Mainland))
Product Summary
The GAL16V8D-25LP is a High Performance E2CMOS PLD. It combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. The GAL16V8D-25LP is capable of emulating any of these PAL architectures with full function/fuse map/parametric compatibility. The applications of the GAL16V8D-25LP are DMA Control, State Machine Control, High Speed Graphics Processing, Standard Logic Speed Upgrade.
Parametrics
GAL16V8D-25LP absolute maximum ratings: (1)Supply voltage VCC:–0.5 to +7V; (2)Input voltage applied:–2.5 to VCC +1.0V; (3)Off-state output voltage applied:–2.5 to VCC +1.0V; (4)Storage Temperature:–65℃ to 150℃; (5)Ambient Temperature with Power Applied:–55℃ to 125℃.
Features
GAL16V8D-25LP features: (1)3.5 ns Maximum Propagation Delay; (2)Fmax = 250 MHz; (3)3.0 ns Maximum from Clock Input to Data Output; (4)UltraMOS Advanced CMOS Technology; (5)Reconfigurable Logic; (6)Reprogrammable Cells; (7)100% Tested/100% Yields; (8)High Speed Electrical Erasure (<100ms); (9)20 Year Data Retention; (10)Maximum Flexibility for Complex Logic Designs; (11)Programmable Output Polarity; (12)Also Emulates 20-pin PAL Devices with Full Function/Fuse Map/Parametric Compatibility; (13)preload and power-on reset of all registers: 100% Functional Testability; (14)electronic signature for identification; (15)lead-free package options.
Diagrams
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 GAL16V8D-25LP |
Lattice |
SPLD - Simple Programmable Logic Devices 5V 16 I/O |
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GAL16V8D-25LPI |
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SPLD - Simple Programmable Logic Devices 16 INPUT 8 OUTPUT 5V LOW POWER 25ns |
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GAL16V8D-25LPNI |
Lattice |
SPLD - Simple Programmable Logic Devices 16 INPUT 8 OUTPUT 5V LOW POWER 25ns |
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GAL16V8D-25LPN |
Lattice |
SPLD - Simple Programmable Logic Devices 16 Input 8 Output 5V Low Power 25ns |
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