AT91SAM7X512-AU

Product Summary

The AT91SAM7X512-AU is a highly integrated Flash microcontroller. It is based on the 32-bit ARM RISC processor. It features 512/256/128 Kbyte high-speed Flash and 128/64/32 Kbyte SRAM, a large set of peripherals, including an 802.3 Ethernet MAC and a CAN controller. The AT91SAM7X512-AU system controller includes a reset controller capable of managing the power-on sequence of the microcontroller and the complete system. Correct device operation can be monitored by a built-in brownout detector and a watchdog running off an integrated RC oscillator. The AT91SAM7X512-AU is a powerful device that provides a flexible, cost-effective solution to many embedded control applications requiring communication over, for example, Ethernet, CAN wired and Zigbee wireless networks.

Parametrics

AT91SAM7X512-AU absolute maximum ratings: (1)Operating Temperature (Industrial):-40℃ to + 85℃; (2)Storage Temperature:-60℃ to + 150℃; (3)Voltage on Input Pins with Respect to Ground:-0.3V to + 5.5V; (4)Maximum Operating Voltage(VDDCORE, and VDDPLL):2.0V; (5)Maximum Operating Voltage(VDDIO, VDDIN and VDDFLASH):4.0V; (6)Total DC Output Current on all I/O lines 100-lead LQFP package:200 mA.

Features

AT91SAM7X512-AU features: (1)Embedded 1.8V Regulator, Drawing up to 100 mA for the Core and External Components; (2)3.3V VDDIO I/O Lines Power Supply, Independent 3.3V VDDFLASH Flash Power Supply; (3)1.8V VDDCORE Core Power Supply with Brownout Detector; (4)One Four-channel 16-bit Power Width Modulation Controller (PWMC); (5)One Two-wire Interface (TWI); (6)Sixty-two Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os ; (7)Input Change Interrupt Capability on Each I/O Line; (8)Individually Programmable Open-drain, Pull-up Resistor and Synchronous Output; (9)Thirteen Peripheral DMA Controller (PDC) Channels; (10)32-bit Free-running Counter with Alarm; (11)Runs Off the Internal RC Oscillator12-bit key-protected Programmable Counter; (12)Provides Reset or Interrupt Signals to the System; (13)Counter May Be Stopped While the Processor is in Debug State or in Idle Mode; (14)2-wire UART and Support for Debug Communication Channel interrupt, Programmable ICE Access Prevention; (15)Mode for General Purpose 2-wire UART Serial Communication; (16)Individually Maskable, Eight-level Priority, Vectored Interrupt Sources; (17)Two External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt Protected.

Diagrams